mirror of https://github.com/YosysHQ/yosys.git
18 lines
165 B
Verilog
18 lines
165 B
Verilog
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module nonblocking (clk,a,c);
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input clk;
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input a;
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output c;
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wire clk;
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wire a;
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reg c;
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reg b;
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always @ (posedge clk )
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begin
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b <= a;
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c <= b;
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end
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endmodule
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