2019-10-18 05:19:59 -05:00
|
|
|
read_verilog ../common/latches.v
|
|
|
|
|
design -save read
|
2019-08-28 14:21:15 -05:00
|
|
|
|
2019-10-18 05:19:59 -05:00
|
|
|
hierarchy -top latchp
|
2019-08-28 14:21:15 -05:00
|
|
|
proc
|
2019-10-03 12:45:53 -05:00
|
|
|
# Can't run any sort of equivalence check because latches are blown to LUTs
|
2019-10-18 05:19:59 -05:00
|
|
|
synth_ice40
|
|
|
|
|
cd latchp # Constrain all select calls below inside the top module
|
|
|
|
|
select -assert-count 1 t:SB_LUT4
|
|
|
|
|
|
|
|
|
|
select -assert-none t:SB_LUT4 %% t:* %D
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
design -load read
|
|
|
|
|
hierarchy -top latchn
|
|
|
|
|
proc
|
|
|
|
|
# Can't run any sort of equivalence check because latches are blown to LUTs
|
|
|
|
|
synth_ice40
|
|
|
|
|
cd latchn # Constrain all select calls below inside the top module
|
|
|
|
|
select -assert-count 1 t:SB_LUT4
|
|
|
|
|
|
|
|
|
|
select -assert-none t:SB_LUT4 %% t:* %D
|
|
|
|
|
|
2019-08-28 14:21:15 -05:00
|
|
|
|
2019-10-18 05:19:59 -05:00
|
|
|
design -load read
|
|
|
|
|
hierarchy -top latchsr
|
|
|
|
|
proc
|
|
|
|
|
# Can't run any sort of equivalence check because latches are blown to LUTs
|
2019-08-19 23:50:05 -05:00
|
|
|
synth_ice40
|
2019-10-18 05:19:59 -05:00
|
|
|
cd latchsr # Constrain all select calls below inside the top module
|
|
|
|
|
select -assert-count 2 t:SB_LUT4
|
|
|
|
|
|
2019-08-22 14:30:49 -05:00
|
|
|
select -assert-none t:SB_LUT4 %% t:* %D
|
