mirror of https://github.com/YosysHQ/yosys.git
37 lines
836 B
Plaintext
37 lines
836 B
Plaintext
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read_verilog <<EOT
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module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
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assign c = a & b;
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endmodule
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EOT
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select -assert-count 1 i:a
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select -assert-count 1 i:b
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select -assert-count 1 o:c
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select -assert-count 3 x:* s:64 %i
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design -save read
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!rm -rf neg.out
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!mkdir neg.out
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simplemap
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write_aiger -map neg.out/neg.map neg.out/neg.aig
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design -reset
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read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
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select -assert-count 1 i:a
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select -assert-count 1 i:b
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select -assert-count 1 o:c
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select -assert-count 3 x:* s:64 %i
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design -load read
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!rm -rf neg.out
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!mkdir neg.out
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simplemap
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write_xaiger -map neg.out/neg.map neg.out/neg.aig
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design -reset
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read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
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select -assert-count 1 i:a
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select -assert-count 1 i:b
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select -assert-count 1 o:c
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select -assert-count 3 x:* s:64 %i
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