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yosys/CODEOWNERS

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Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
## CODE NOTIFICATIONS
# Register yourself here to be notified about modifications
# for any files you have an interest in/know your way around.
# Each line is a file pattern followed by one or more users.
# Both github usernames and email addresses are supported.
# Order is important; the last matching pattern takes the most
# precedence. Previous matches will not be applied.
# PATH (can use glob) USERNAME(S)
Add workflows and CODEOWNERS and fixed gitignore
2024-04-11 07:56:00 -05:00
CODEOWNERS @nakengelhardt
Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
passes/cmds/scratchpad.cc @nakengelhardt
frontends/rpc/ @whitequark
backends/cxxrtl/ @whitequark
passes/cmds/bugpoint.cc @whitequark
passes/techmap/flowmap.cc @whitequark
passes/opt/opt_lut.cc @whitequark
codeowners: adopt ABC9 and update intel_alm username
2022-06-20 09:01:52 -05:00
passes/techmap/abc9*.cc @eddiehung @Ravenslofty
abc9: fix SCC issues (#2694) * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
2021-03-30 00:01:57 -05:00
backends/aiger/xaiger.cc @eddiehung
codeowners: adopting docs folder
2024-01-26 16:32:08 -06:00
docs/ @KrystalDelusion
Add workflows and CODEOWNERS and fixed gitignore
2024-04-11 07:56:00 -05:00
.github/workflows/*.yml @mmicko
Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
## External Contributors
# Only users with write permission to the repository get review
# requests automatically, but we add information for other
# contributors here too, so we know who to ask to take a look.
# These still override previous lines, so be careful not to
# accidentally disable any of the above rules.
CODEOWNERS: add @zachjs as Verilog/AST frontend owner
2020-12-26 23:00:04 -06:00
frontends/verilog/ @zachjs
frontends/ast/ @zachjs
codeowners: adopt ABC9 and update intel_alm username
2022-06-20 09:01:52 -05:00
techlibs/intel_alm/ @Ravenslofty
Update CODEOWNERS
2021-11-08 09:59:45 -06:00
techlibs/gowin/ @pepijndevos
Update CHANGELOG and CODEOWNERS
2021-12-01 01:42:37 -06:00
techlibs/gatemate/ @pu-cc
Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
# pyosys
misc/*.py @btut
backends/firrtl @ucbjrl @azidar
passes/sat/qbfsat.cc @boqwxp
qbfsat: Clean up and refactor data structures into `qbfsat.h`.
2020-06-29 17:06:43 -05:00
passes/sat/qbfsat.h @boqwxp
Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
passes/cmds/exec.cc @boqwxp
glift: Add CODEOWNERS entry.
2020-06-19 14:10:06 -05:00
passes/cmds/glift.cc @boqwxp
Add codeowners file (#2098)
2020-06-04 11:20:08 -05:00
passes/cmds/printattrs.cc @boqwxp