mirror of https://github.com/YosysHQ/yosys.git
32 lines
723 B
Systemverilog
32 lines
723 B
Systemverilog
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module pass_through #(
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parameter WIDTH = 1
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) (
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input logic [WIDTH-1:0] inp,
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output logic [WIDTH-1:0] out
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);
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assign out = inp;
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endmodule
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module gate (
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input logic inp,
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output logic [63:0]
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out1, out2, out3, out4
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);
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pass_through #(40) pt1('1, out1);
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pass_through #(40) pt2(inp ? '1 : '0, out2);
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pass_through #(40) pt3(inp ? '1 : 2'b10, out3);
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pass_through #(40) pt4(inp ? '1 : inp, out4);
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endmodule
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module gold (
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input logic inp,
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output logic [63:0]
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out1, out2, out3, out4
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);
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localparam ONES = 40'hFF_FFFF_FFFF;
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pass_through #(40) pt1(ONES, out1);
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pass_through #(40) pt2(inp ? ONES : 0, out2);
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pass_through #(40) pt3(inp ? ONES : 2'sb10, out3);
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pass_through #(40) pt4(inp ? ONES : inp, out4);
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endmodule
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