yosys/tests/sim/sim_aldffe.ys

7 lines
142 B
Plaintext
Raw Permalink Normal View History

2022-02-15 02:35:53 -06:00
read_verilog aldffe.v
proc
opt_dff
stat
select -assert-count 1 t:$aldffe
sim -clock clk -r tb_aldffe.fst -scope tb_aldffe.uut -sim-cmp aldffe