2022-02-02 06:22:44 -06:00
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module ram_memory(
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input clk,
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input [11:0] addr,
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input [7:0] data_in,
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input we,
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output reg [7:0] data_out
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);
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reg [7:0] store[0:4095] /* verilator public_flat */;
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initial
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begin
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store[0] <= 8'b11100001; // MOV DS,2
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store[1] <= 8'b00000010; //
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store[2] <= 8'b01010100; // LOAD R1,[R0]
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store[3] <= 8'b00110001; // INC R1
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store[4] <= 8'b00110001; // INC R1
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store[5] <= 8'b01100001; // STORE [R0],R1
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store[6] <= 8'b11010001; // OUT [0],R1
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store[7] <= 8'b00000000; //
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store[8] <= 8'b00110001; // INC R1
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store[9] <= 8'b10100001; // CALL 0x100
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store[10] <= 8'b00000000; //
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store[11] <= 8'b01111111; // HLT
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store[256] <= 8'b11010001; // OUT [0],R1
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store[257] <= 8'b00000000; //
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store[258] <= 8'b01111110; // RET
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2022-03-14 09:39:11 -05:00
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store[512] <= 8'b00000000;
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2022-02-02 06:22:44 -06:00
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end
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always @(posedge clk)
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if (we)
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store[addr] <= data_in;
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else
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data_out <= store[addr];
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endmodule
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