mirror of https://github.com/YosysHQ/yosys.git
88 lines
1.7 KiB
Verilog
88 lines
1.7 KiB
Verilog
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module test_001(clk, a, a_old, b);
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// test case taken from:
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// http://www.reddit.com/r/yosys/comments/1wvpj6/trouble_with_assertions_and_sat_solver/
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input wire clk;
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input wire a;
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output reg a_old = 0;
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output reg b = 1;
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wire assertion = (a_old != b);
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always @(posedge clk) begin
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a_old <= a;
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b <= !a;
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assert(a_old != b);
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end
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endmodule
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module test_002(clk, a, a_old, b);
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// copy from test_001 with modifications
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input wire clk;
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input wire a;
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output reg a_old = 0;
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output reg b = 0; // <-- this will fail
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wire assertion = (a_old != b);
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always @(posedge clk) begin
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a_old <= a;
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b <= !a;
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assert(a_old != b);
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end
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endmodule
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module test_003(clk, a, a_old, b);
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// copy from test_001 with modifications
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input wire clk;
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input wire a;
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output reg a_old = 0;
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output reg b; // <-- this will fail
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wire assertion = (a_old != b);
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always @(posedge clk) begin
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a_old <= a;
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b <= !a;
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assert(a_old != b);
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end
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endmodule
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module test_004(clk, a, a_old, b);
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// copy from test_001 with modifications
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input wire clk;
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input wire a;
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output reg a_old = 0;
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output reg b = 1;
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wire assertion = (a_old != b);
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always @(posedge clk) begin
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a_old <= a;
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b <= !a;
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assert(a_old == b); // <-- this will fail
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end
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endmodule
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module test_005(clk, a, a_old, b);
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// copy from test_001 with modifications
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input wire clk;
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input wire a;
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output reg a_old = 1; // <-- inverted, no problem
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output reg b = 0;
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wire assertion = (a_old != b);
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always @(posedge clk) begin
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a_old <= a;
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b <= !a;
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assert(a_old != b);
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end
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endmodule
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