mirror of https://github.com/YosysHQ/yosys.git
14 lines
354 B
Plaintext
14 lines
354 B
Plaintext
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read_verilog opt_share_diff_port_widths.v
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proc;;
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copy opt_share_test merged
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alumacc merged
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opt merged
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opt_share merged
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opt_clean merged
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miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
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sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
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select -assert-count 2 -module merged t:$alu
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