mirror of https://github.com/YosysHQ/yosys.git
46 lines
1.9 KiB
Plaintext
46 lines
1.9 KiB
Plaintext
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### Never-toggling CLK removal.
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read_verilog -icells <<EOT
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module top(...);
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input EN;
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input [1:0] D;
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(* init = 18'h15555 *)
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output [17:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(1'b0), .D(D), .Q(Q[1:0]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(1'bx), .ARST(ARST), .D(D), .Q(Q[5:4]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(1'b0), .EN(EN), .ARST(ARST), .D(D), .Q(Q[7:6]));
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(1'b1), .SRST(SRST), .D(D), .Q(Q[9:8]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(1'bx), .EN(EN), .SRST(SRST), .D(D), .Q(Q[11:10]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(1'bx), .EN(EN), .SRST(SRST), .D(D), .Q(Q[13:12]));
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$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(1'bx), .EN(EN), .SET(SET), .CLR(CLR), .D(D), .Q(Q[17:16]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 2 t:$dlatch
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select -assert-count 2 t:$sr
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select -assert-none t:$dlatch t:$sr %% %n t:* %i
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 4 t:$_DLATCH_?_
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select -assert-count 4 t:$_SR_??_
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select -assert-none t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
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