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16 lines
203 B
Plaintext
16 lines
203 B
Plaintext
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read_verilog <<EOT
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module top(
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input wire shift,
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input wire [4:0] data,
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output wire out
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);
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wire [1:0] shift2 = shift - 1'b1;
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assign out = data >> shift2;
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endmodule
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EOT
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equiv_opt -assert peepopt
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