mirror of https://github.com/YosysHQ/yosys.git
15 lines
266 B
Verilog
15 lines
266 B
Verilog
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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MULT18X18 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.P(Y)
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);
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endmodule
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