mirror of https://github.com/YosysHQ/yosys.git
533 lines
12 KiB
Verilog
533 lines
12 KiB
Verilog
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module $__XILINX_BLOCKRAM_ (...);
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parameter INIT = 0;
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parameter OPTION_USE_BE = 0;
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parameter PORT_A_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_USED = 1;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_A_RD_INIT_VALUE = 0;
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parameter PORT_A_RD_SRST_VALUE = 0;
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parameter PORT_B_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_RD_INIT_VALUE = 0;
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parameter PORT_B_RD_SRST_VALUE = 0;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_A_RD_SRST;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [13:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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input PORT_B_RD_SRST;
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`include "brams_defs.vh"
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`define PARAMS_DP \
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`PARAMS_INIT_18 \
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.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
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.SRVAL_A(SRVAL_A), \
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.SRVAL_B(SRVAL_B), \
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.INIT_A(INIT_A), \
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.INIT_B(INIT_B),
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`define PARAMS_DP_SWAP \
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`PARAMS_INIT_18 \
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.WRITE_MODE_A(PORT_B_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_A_OPTION_WRITE_MODE), \
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.SRVAL_A(SRVAL_B), \
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.SRVAL_B(SRVAL_A), \
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.INIT_A(INIT_B), \
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.INIT_B(INIT_A),
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`define PARAMS_SP \
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`PARAMS_INIT_18 \
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.WRITE_MODE(PORT_A_OPTION_WRITE_MODE), \
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.SRVAL(SRVAL_A), \
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.INIT(INIT_A),
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`define PORTS_DP(addr_slice_a, addr_slice_b) \
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.CLKA(PORT_A_CLK), \
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.ENA(PORT_A_CLK_EN), \
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.WEA(PORT_A_WR_EN), \
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.SSRA(PORT_A_RD_SRST), \
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.ADDRA(PORT_A_ADDR addr_slice_a), \
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.DOA(DO_A), \
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.DIA(DI_A), \
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.CLKB(PORT_B_CLK), \
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.ENB(PORT_B_CLK_EN), \
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.WEB(PORT_B_WR_EN), \
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.SSRB(PORT_B_RD_SRST), \
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.ADDRB(PORT_B_ADDR addr_slice_b), \
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.DOB(DO_B), \
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.DIB(DI_B),
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`define PORTS_DP_SWAP(addr_slice_a, addr_slice_b) \
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.CLKB(PORT_A_CLK), \
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.ENB(PORT_A_CLK_EN), \
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.WEB(PORT_A_WR_EN), \
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.SSRB(PORT_A_RD_SRST), \
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.ADDRB(PORT_A_ADDR addr_slice_a), \
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.DOB(DO_A), \
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.DIB(DI_A), \
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.CLKA(PORT_B_CLK), \
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.ENA(PORT_B_CLK_EN), \
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.WEA(PORT_B_WR_EN), \
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.SSRA(PORT_B_RD_SRST), \
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.ADDRA(PORT_B_ADDR addr_slice_b), \
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.DOA(DO_B), \
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.DIA(DI_B),
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`define PORTS_SP(addr_slice) \
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.CLK(PORT_A_CLK), \
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.EN(PORT_A_CLK_EN), \
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.WE(PORT_A_WR_EN), \
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.SSR(PORT_A_RD_SRST), \
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.ADDR(PORT_A_ADDR addr_slice), \
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.DO(DO_A), \
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.DI(DI_A),
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localparam [PORT_A_WIDTH-1:0] SRVAL_A = ival(PORT_A_WIDTH, PORT_A_RD_SRST_VALUE);
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localparam [PORT_B_WIDTH-1:0] SRVAL_B = ival(PORT_B_WIDTH, PORT_B_RD_SRST_VALUE);
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localparam [PORT_A_WIDTH-1:0] INIT_A = ival(PORT_A_WIDTH, PORT_A_RD_INIT_VALUE);
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localparam [PORT_B_WIDTH-1:0] INIT_B = ival(PORT_B_WIDTH, PORT_B_RD_INIT_VALUE);
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`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
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`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
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`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
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`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
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generate
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if (OPTION_USE_BE) begin
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if (!PORT_B_USED) begin
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case (PORT_A_WIDTH)
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9: RAMB16_S9 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:3])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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18: RAMB16BWE_S18 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:4])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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36: RAMB16BWE_S36 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:5])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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endcase
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end else begin
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case (PORT_A_WIDTH)
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9: case(PORT_B_WIDTH)
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9: RAMB16_S9_S9 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:3], [13:3])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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18: RAMB16BWE_S9_S18 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:3], [13:4])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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36: RAMB16BWE_S9_S36 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:3], [13:5])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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endcase
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18: case(PORT_B_WIDTH)
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9: RAMB16BWE_S9_S18 #(
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`PARAMS_DP_SWAP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP_SWAP([13:4], [13:3])
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.DIPA(DIP_B), .DOPA(DOP_B),
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.DIPB(DIP_A), .DOPB(DOP_A),
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);
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18: RAMB16BWE_S18_S18 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:4], [13:4])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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36: RAMB16BWE_S18_S36 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:4], [13:5])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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endcase
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36: case(PORT_B_WIDTH)
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9: RAMB16BWE_S9_S36 #(
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`PARAMS_DP_SWAP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP_SWAP([13:5], [13:3])
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.DIPA(DIP_B), .DOPA(DOP_B),
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.DIPB(DIP_A), .DOPB(DOP_A),
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);
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18: RAMB16BWE_S18_S36 #(
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`PARAMS_DP_SWAP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP_SWAP([13:5], [13:4])
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.DIPA(DIP_B), .DOPA(DOP_B),
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.DIPB(DIP_A), .DOPB(DOP_A),
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);
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36: RAMB16BWE_S36_S36 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:5], [13:5])
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.DIPA(DIP_A), .DOPA(DOP_A),
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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endcase
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endcase
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end
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end else begin
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if (!PORT_B_USED) begin
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case (PORT_A_WIDTH)
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1: RAMB16_S1 #(
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`PARAMS_SP
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:0])
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);
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2: RAMB16_S2 #(
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`PARAMS_SP
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:1])
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);
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4: RAMB16_S4 #(
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`PARAMS_SP
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:2])
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);
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9: RAMB16_S9 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:3])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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18: RAMB16_S18 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:4])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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36: RAMB16_S36 #(
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`PARAMS_SP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_SP([13:5])
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.DIP(DIP_A),
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.DOP(DOP_A),
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);
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endcase
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end else begin
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case (PORT_A_WIDTH)
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1: case(PORT_B_WIDTH)
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1: RAMB16_S1_S1 #(
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`PARAMS_DP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:0])
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);
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2: RAMB16_S1_S2 #(
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`PARAMS_DP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:1])
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);
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4: RAMB16_S1_S4 #(
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`PARAMS_DP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:2])
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);
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9: RAMB16_S1_S9 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:3])
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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18: RAMB16_S1_S18 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:4])
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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36: RAMB16_S1_S36 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:0], [13:5])
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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endcase
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2: case(PORT_B_WIDTH)
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1: RAMB16_S1_S2 #(
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`PARAMS_DP_SWAP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP_SWAP([13:1], [13:0])
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);
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2: RAMB16_S2_S2 #(
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`PARAMS_DP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:1], [13:1])
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);
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4: RAMB16_S2_S4 #(
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`PARAMS_DP
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:1], [13:2])
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);
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9: RAMB16_S2_S9 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:1], [13:3])
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.DIPB(DIP_B), .DOPB(DOP_B),
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);
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18: RAMB16_S2_S18 #(
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`PARAMS_DP
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`PARAMS_INITP_18
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) _TECHMAP_REPLACE_ (
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`PORTS_DP([13:1], [13:4])
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.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
36: RAMB16_S2_S36 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:1], [13:5])
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
endcase
|
||
|
|
4: case(PORT_B_WIDTH)
|
||
|
|
1: RAMB16_S1_S4 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:2], [13:0])
|
||
|
|
);
|
||
|
|
2: RAMB16_S2_S4 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:2], [13:1])
|
||
|
|
);
|
||
|
|
4: RAMB16_S4_S4 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:2], [13:2])
|
||
|
|
);
|
||
|
|
9: RAMB16_S4_S9 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:2], [13:3])
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
18: RAMB16_S4_S18 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:2], [13:4])
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
36: RAMB16_S4_S36 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:2], [13:5])
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
endcase
|
||
|
|
9: case(PORT_B_WIDTH)
|
||
|
|
1: RAMB16_S1_S9 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:3], [13:0])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
2: RAMB16_S2_S9 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:3], [13:1])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
4: RAMB16_S4_S9 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:3], [13:2])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
9: RAMB16_S9_S9 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:3], [13:3])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
18: RAMB16_S9_S18 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:3], [13:4])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
36: RAMB16_S9_S36 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:3], [13:5])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
endcase
|
||
|
|
18: case(PORT_B_WIDTH)
|
||
|
|
1: RAMB16_S1_S18 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:4], [13:0])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
2: RAMB16_S2_S18 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:4], [13:1])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
4: RAMB16_S4_S18 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:4], [13:2])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
9: RAMB16_S9_S18 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:4], [13:3])
|
||
|
|
.DIPA(DIP_B), .DOPA(DOP_B),
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
18: RAMB16_S18_S18 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:4], [13:4])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
36: RAMB16_S18_S36 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:4], [13:5])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
endcase
|
||
|
|
36: case(PORT_B_WIDTH)
|
||
|
|
1: RAMB16_S1_S36 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:5], [13:0])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
2: RAMB16_S2_S36 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:5], [13:1])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
4: RAMB16_S4_S36 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:5], [13:2])
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
9: RAMB16_S9_S36 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:5], [13:3])
|
||
|
|
.DIPA(DIP_B), .DOPA(DOP_B),
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
18: RAMB16_S18_S36 #(
|
||
|
|
`PARAMS_DP_SWAP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP_SWAP([13:5], [13:4])
|
||
|
|
.DIPA(DIP_B), .DOPA(DOP_B),
|
||
|
|
.DIPB(DIP_A), .DOPB(DOP_A),
|
||
|
|
);
|
||
|
|
36: RAMB16_S36_S36 #(
|
||
|
|
`PARAMS_DP
|
||
|
|
`PARAMS_INITP_18
|
||
|
|
) _TECHMAP_REPLACE_ (
|
||
|
|
`PORTS_DP([13:5], [13:5])
|
||
|
|
.DIPA(DIP_A), .DOPA(DOP_A),
|
||
|
|
.DIPB(DIP_B), .DOPB(DOP_B),
|
||
|
|
);
|
||
|
|
endcase
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|