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yosys/techlibs/intel_alm/common/dff_map.v

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synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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`default_nettype none
synth_intel_alm: Use dfflegalize.
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// D flip-flop with async reset and enable
module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
synth_intel_alm: Use dfflegalize.
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(R), .ENA(E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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endmodule
synth_intel_alm: Use dfflegalize.
2020-06-30 20:31:34 -05:00
// D flip-flop with sync reset and enable (enable has priority)
module \$_SDFFCE_PP0P_ (input D, C, R, E, output Q);
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
synth_intel_alm: Use dfflegalize.
2020-06-30 20:31:34 -05:00
MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(E), .SCLR(R), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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endmodule