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yosys/techlibs/intel_alm/common/bram_m10k.txt

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intel_alm: M10K write-enable is negative-true
2022-03-09 10:40:32 -06:00
bram $__MISTRAL_M10K
intel_alm: enable M10K initialisation
2023-05-25 11:48:48 -05:00
init 1
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
abits 13 @D8192x1
dbits 1 @D8192x1
abits 12 @D4096x2
dbits 2 @D4096x2
intel_alm: disable 256x40 M10K mode This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
2021-12-21 12:11:45 -06:00
abits 11 @D2048x5
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
dbits 5 @D2048x5
intel_alm: disable 256x40 M10K mode This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
2021-12-21 12:11:45 -06:00
abits 10 @D1024x10
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
dbits 10 @D1024x10
intel_alm: disable 256x40 M10K mode This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
2021-12-21 12:11:45 -06:00
abits 9 @D512x20
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
dbits 20 @D512x20
intel_alm: re-enable 8x40-bit M10K support
2023-05-28 23:49:53 -05:00
abits 8 @D256x40
dbits 40 @D256x40
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
groups 2
ports 1 1
wrmode 1 0
# read enable; write enable + byte enables (only for multiples of 8)
enable 1 1
transp 0 0
clocks 1 1
clkpol 1 1
endbram
intel_alm: M10K write-enable is negative-true
2022-03-09 10:40:32 -06:00
match $__MISTRAL_M10K
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
min efficiency 5
make_transp
endmatch