mirror of https://github.com/YosysHQ/yosys.git
16 lines
248 B
Verilog
16 lines
248 B
Verilog
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module $_DLATCH_P_(input E, input D, output Q);
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GP_DLATCH _TECHMAP_REPLACE_ (
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.D(D),
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.nCLK(!E),
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.Q(Q)
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);
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endmodule
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module $_DLATCH_N_(input E, input D, output Q);
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GP_DLATCH _TECHMAP_REPLACE_ (
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.D(D),
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.nCLK(E),
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.Q(Q)
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);
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endmodule
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