mirror of https://github.com/YosysHQ/yosys.git
57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
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input A, B, C, D, E, F, G, H, S, T, U;
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output Y;
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CC_MX8 _TECHMAP_REPLACE_ (
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.D0(A), .D1(B), .D2(C), .D3(D),
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.D4(E), .D5(F), .D6(G), .D7(H),
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.S0(S), .S1(T), .S2(U),
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.Y(Y)
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);
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endmodule
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module \$_MUX4_ (A, B, C, D, S, T, Y);
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input A, B, C, D, S, T;
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output Y;
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CC_MX4 _TECHMAP_REPLACE_ (
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.D0(A), .D1(B), .D2(C), .D3(D),
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.S0(S), .S1(T),
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.Y(Y)
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);
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endmodule
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/*
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module \$_MUX_ (A, B, S, Y);
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input A, B, S;
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output Y;
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CC_MX2 _TECHMAP_REPLACE_ (
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.D0(A), .D1(B), .S0(S),
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.Y(Y)
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);
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endmodule
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*/
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