mirror of https://github.com/YosysHQ/yosys.git
70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO, CI};
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1)
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begin: slice
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CC_ADDF addf_i (
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.A(AA[i]),
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.B(BB[i]),
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.CI(C[i]),
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.CO(CO[i]),
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.S(Y[i])
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);
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end
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endgenerate
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assign X = AA ^ BB;
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endmodule
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