mirror of https://github.com/YosysHQ/yosys.git
15 lines
300 B
Verilog
15 lines
300 B
Verilog
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module scrambler(
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input clk, rst, in_bit,
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output reg out_bit
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);
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reg [31:0] xs;
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always @(posedge clk) begin
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if (rst)
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xs = 1;
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xs = xs ^ (xs << 13);
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xs = xs ^ (xs >> 17);
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xs = xs ^ (xs << 5);
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out_bit <= in_bit ^ xs[0];
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end
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endmodule
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