mirror of https://github.com/YosysHQ/yosys.git
22 lines
689 B
Systemverilog
22 lines
689 B
Systemverilog
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// Taken from: https://github.com/YosysHQ/yosys/issues/2867
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`define MIN(x, y) ((x) < (y) ? (x) : (y))
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`define CEIL_DIV(x, y) (((x) / (y)) + `MIN((x) % (y), 1))
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module pad_msg1 (input logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] x,
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output logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] y);
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assign y[63:0] = x;
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endmodule
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module pad_msg2 (input logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] x,
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output logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] y);
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assign y[63:0] = x;
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endmodule
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module top(...);
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`define add(x) x +
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input [3:0] A;
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output [3:0] B;
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assign B = `add(`add(3)A)A;
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endmodule
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