yosys/tests/verilog/for_decl_shadow.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog -sv for_decl_shadow.sv
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert
sv: support declaration in procedural for initialization In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable. 2021-08-30 12:35:36 -05:00			`read_verilog -sv for_decl_shadow.sv`
			`hierarchy`
			`proc`
			`equiv_make gold gate equiv`
			`equiv_simple`
			`equiv_status -assert`