mirror of https://github.com/YosysHQ/yosys.git
16 lines
252 B
Plaintext
16 lines
252 B
Plaintext
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read_verilog -sv <<EOF
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module top(input wire x, y, output reg z);
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function automatic f;
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input inp;
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for (int i = 0; i < 1; i++)
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f = inp + 0;
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endfunction
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always_comb
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if (y)
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z = f(x);
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else
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z = 0;
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endmodule
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EOF
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proc
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