mirror of https://github.com/YosysHQ/yosys.git
17 lines
233 B
Plaintext
17 lines
233 B
Plaintext
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read_verilog -sv <<EOF
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module top;
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logic [4:0] x;
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logic z;
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assign z = 1'b1;
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always_comb begin
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x = '0;
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if (z) begin
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for (int i = 0; i < 5; i++) begin
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x[i] = 1'b1;
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end
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end
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end
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endmodule
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EOF
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proc
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