mirror of https://github.com/YosysHQ/yosys.git
17 lines
279 B
Plaintext
17 lines
279 B
Plaintext
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logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
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read_verilog <<EOF
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module top(
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output out
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);
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assign out =
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{1024 {
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{1024 {
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{1024 {
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1'b1
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}}
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}}
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}}
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;
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endmodule
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EOF
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