mirror of https://github.com/YosysHQ/yosys.git
21 lines
355 B
Plaintext
21 lines
355 B
Plaintext
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read_verilog -specify <<EOT
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(* abc9_box, blackbox*)
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module box(input clk, d, output reg q, output do);
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parameter P = 0;
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always @(posedge clk)
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q <= d;
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assign do = d;
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specify
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(posedge clk => (q : d)) = 1;
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(d => do) = 1;
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endspecify
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endmodule
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module top(input clk, d, output q);
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box i1(clk, d, q);
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endmodule
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EOT
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hierarchy
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abc9 -lut 4
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abc9 -lut 4
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