mirror of https://github.com/YosysHQ/yosys.git
12 lines
243 B
Plaintext
12 lines
243 B
Plaintext
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# Check wires driven by constants are kept
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read_verilog <<EOT
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module top(output wire [7:0] y);
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assign y = 27;
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endmodule
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EOT
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equiv_opt -assert bufnorm
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design -load postopt
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select -assert-count 1 t:$buf
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select -assert-count 1 w:y %ci t:$buf %i
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