yosys/tests/sva/sva_value_change_changed.sv

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Systemverilog
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module top (
input clk,
input a, b
);
default clocking @(posedge clk); endclocking
assert property (
$changed(b)
);
wire x = 'x;
`ifndef FAIL
assume property (
b !== x ##1 $changed(b)
);
`endif
endmodule