mirror of https://github.com/YosysHQ/yosys.git
35 lines
505 B
Systemverilog
35 lines
505 B
Systemverilog
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module top (
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input clk,
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input reset,
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input ping,
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input [1:0] cfg,
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output reg pong
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);
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reg [2:0] cnt;
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localparam integer maxdelay = 8;
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always @(posedge clk) begin
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if (reset) begin
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cnt <= 0;
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pong <= 0;
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end else begin
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cnt <= cnt - |cnt;
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pong <= cnt == 1;
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if (ping) cnt <= 4 + cfg;
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end
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end
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assert property (
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@(posedge clk)
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disable iff (reset)
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not (ping ##1 !pong [*maxdelay])
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);
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`ifndef FAIL
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assume property (
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@(posedge clk)
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not (cnt && ping)
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);
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`endif
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endmodule
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