mirror of https://github.com/YosysHQ/yosys.git
7 lines
131 B
Plaintext
7 lines
131 B
Plaintext
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read_verilog dlatch.v
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proc
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opt_dff
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stat
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select -assert-count 1 t:$dlatch
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sim -r tb_dlatch.fst -scope tb_dlatch.uut -sim-cmp dlatch
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