mirror of https://github.com/YosysHQ/yosys.git
49 lines
873 B
Plaintext
49 lines
873 B
Plaintext
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# Create stimulus file
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read_verilog <<EOT
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module top (clk, reset, cnt);
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input clk;
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input reset;
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output [7:0] cnt;
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reg [7:0] cnt;
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endmodule
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EOT
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prep -top top;
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sim -clock clk -reset reset -fst stimulus.fst -n 10
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design -reset
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# Counter implementation
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read_verilog <<EOT
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module top (clk, reset, cnt);
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input clk;
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input reset;
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output [7:0] cnt;
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reg [7:0] cnt;
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always @(posedge clk)
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if (!reset)
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cnt = cnt + 1;
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else
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cnt = 0;
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endmodule
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EOT
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prep -top top;
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# Simulate with stimulus
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sim -clock clk -scope top -r stimulus.fst
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# Stimulus does not have counter values
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# x in FST can match any value in simulation
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sim -clock clk -scope top -r stimulus.fst -sim-gate
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# Stimulus does not have counter values
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# x in simulation can match any value in FST
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# so we expect error
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logger -expect error "Signal difference" 1
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sim -clock clk -scope top -r stimulus.fst -sim-gold
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