mirror of https://github.com/YosysHQ/yosys.git
32 lines
698 B
Verilog
32 lines
698 B
Verilog
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module grom_computer
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(input clk, // Main Clock
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input reset, // reset
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output hlt,
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output reg[7:0] display_out
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);
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wire [11:0] addr;
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wire [7:0] memory_out;
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wire [7:0] memory_in;
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wire mem_enable;
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wire we;
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wire ioreq;
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grom_cpu cpu(.clk(clk),.reset(reset),.addr(addr),.data_in(memory_out),.data_out(memory_in),.we(we),.ioreq(ioreq),.hlt(hlt));
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assign mem_enable = we & ~ioreq;
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ram_memory memory(.clk(clk),.addr(addr),.data_in(memory_in),.we(mem_enable),.data_out(memory_out));
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always @(posedge clk)
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begin
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if(ioreq==1 && we==1)
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begin
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display_out <= memory_in;
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`ifdef DISASSEMBLY
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$display("Display output : %h", memory_in);
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`endif
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end
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end
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endmodule
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