mirror of https://github.com/YosysHQ/yosys.git
13 lines
167 B
Verilog
13 lines
167 B
Verilog
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module top (
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input clk,
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output reg [7:0] cnt
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);
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initial cnt = 0;
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always @(posedge clk) begin
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if (cnt < 20)
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cnt <= cnt + 1;
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else
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cnt <= 0;
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end
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endmodule
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