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15 lines
144 B
Plaintext
15 lines
144 B
Plaintext
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read_verilog -icells << EOT
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module top(...);
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input A;
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output Y;
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$_XNOR_ x (.A(A), .B(A), .Y(Y));
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endmodule
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EOT
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equiv_opt -assert opt_expr
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