mirror of https://github.com/YosysHQ/yosys.git
17 lines
224 B
Plaintext
17 lines
224 B
Plaintext
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read_verilog <<EOT
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module test (
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input [1:0] a,
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input [1:0] b,
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output [5:0] y
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);
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wire [5:0] aa = {a, 4'h0};
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wire [5:0] bb = {b, 4'h0};
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assign y = aa * bb;
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endmodule
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EOT
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equiv_opt -assert opt_expr
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