mirror of https://github.com/YosysHQ/yosys.git
18 lines
296 B
Plaintext
18 lines
296 B
Plaintext
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read_verilog << EOT
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module top(input clk, input [3:0] addr, output reg [0:0] dout);
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reg [1:0] mem[0:15];
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initial begin
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mem[0] = 2'b00;
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mem[1] = 2'b01;
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mem[2] = 2'b10;
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mem[3] = 2'b11;
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end
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always @(posedge clk)
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dout <= mem[addr];
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endmodule
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EOT
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prep -rdff
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select -assert-none t:$dff
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