mirror of https://github.com/YosysHQ/yosys.git
30 lines
434 B
Verilog
30 lines
434 B
Verilog
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// expect-wr-ports 3
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// expect-rd-ports 1
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// expect-wr-wide-continuation 3'010
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module test(
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input clk,
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input we1, we2,
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input [5:0] ra,
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input [4:0] wa1,
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input [5:0] wa2,
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input [15:0] wd1,
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input [7:0] wd2,
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output [7:0] rd
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);
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reg [7:0] mem[0:63];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[{wa1, 1'b0}] <= wd1[7:0];
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if (we2)
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mem[wa2] <= wd2;
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if (we1)
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mem[{wa1, 1'b1}] <= wd1[15:8];
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end
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endmodule
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