mirror of https://github.com/YosysHQ/yosys.git
39 lines
881 B
Verilog
39 lines
881 B
Verilog
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module RAM_BLOCK_TDP(
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input PORT_A_CLK,
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input PORT_A_WR_EN,
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input [9:0] PORT_A_ADDR,
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input [15:0] PORT_A_WR_DATA,
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output reg [15:0] PORT_A_RD_DATA,
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input PORT_B_CLK,
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input PORT_B_WR_EN,
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input [9:0] PORT_B_ADDR,
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input [15:0] PORT_B_WR_DATA,
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output reg [15:0] PORT_B_RD_DATA
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);
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parameter INIT = 0;
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parameter PORT_A_WIDTH = 1;
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parameter PORT_B_WIDTH = 1;
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parameter PORT_A_CLK_POL = 0;
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parameter PORT_B_CLK_POL = 0;
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reg [2**10-1:0] mem = INIT;
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always @(negedge (PORT_A_CLK ^ PORT_A_CLK_POL)) begin
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if (PORT_A_WR_EN) begin
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mem[PORT_A_ADDR+:PORT_A_WIDTH] <= PORT_A_WR_DATA;
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end else begin
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PORT_A_RD_DATA <= mem[PORT_A_ADDR+:PORT_A_WIDTH];
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end
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end
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always @(negedge (PORT_B_CLK ^ PORT_B_CLK_POL)) begin
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if (PORT_B_WR_EN) begin
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mem[PORT_B_ADDR+:PORT_B_WIDTH] <= PORT_B_WR_DATA;
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end else begin
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PORT_B_RD_DATA <= mem[PORT_B_ADDR+:PORT_B_WIDTH];
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end
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end
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endmodule
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