yosys/tests/liberty/XNOR2X1.lib.verilogsim.ok

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2024-08-13 11:36:31 -05:00
module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
endmodule