mirror of https://github.com/YosysHQ/yosys.git
13 lines
277 B
Verilog
13 lines
277 B
Verilog
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// test_simulation_seq_ff_1_test.v
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module f1_test(input in, input clk, output reg out);
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always @(posedge clk)
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out <= in;
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endmodule
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// test_simulation_seq_ff_2_test.v
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module f2_test(input in, input clk, output reg out);
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always @(negedge clk)
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out <= in;
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endmodule
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