mirror of https://github.com/YosysHQ/yosys.git
18 lines
373 B
Verilog
18 lines
373 B
Verilog
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// test_simulation_buffer_1_test.v
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module f1_test(input in, output out);
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assign out = in;
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endmodule
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// test_simulation_buffer_2_test.v
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module f2_test(input [1:0] in, output [1:0] out);
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assign out[0] = in[0];
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assign out[1] = in[1];
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endmodule
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// test_simulation_buffer_3_test.v
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module f3_test(input in, output [1:0] out);
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assign out[0] = in;
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assign out[1] = in;
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endmodule
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