mirror of https://github.com/YosysHQ/yosys.git
23 lines
540 B
Verilog
23 lines
540 B
Verilog
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module top (clk, write_enable, read_enable, write_data, addr, read_data);
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parameter DATA_WIDTH = 8;
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parameter ADDR_WIDTH = 8;
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parameter SKIP_RDEN = 1;
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input clk;
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input write_enable, read_enable;
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input [DATA_WIDTH - 1 : 0] write_data;
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input [ADDR_WIDTH - 1 : 0] addr;
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output [DATA_WIDTH - 1 : 0] read_data;
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(* ram_style = "huge" *)
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[addr] <= write_data;
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else if (SKIP_RDEN || read_enable)
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read_data <= mem[addr];
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end
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endmodule
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