mirror of https://github.com/YosysHQ/yosys.git
11 lines
293 B
Plaintext
11 lines
293 B
Plaintext
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read_verilog <<EOT
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module prim_test(input [7:0] a, b, output [7:0] q);
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AND and_i (.A(a), .B(b), .Y(q));
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endmodule
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EOT
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# Test adding custom primitives and techmap rules
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synth_fabulous -top prim_test -extra-plib custom_prims.v -extra-map custom_map.v
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cd prim_test
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select -assert-count 1 t:ALU
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