mirror of https://github.com/YosysHQ/yosys.git
9 lines
164 B
Verilog
9 lines
164 B
Verilog
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(* blackbox *)
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module AND(input [7:0] A, B, output [7:0] Y);
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endmodule
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(* blackbox *)
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module ALU(input [7:0] A, B, output [7:0] Y);
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parameter MODE = "";
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endmodule
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