mirror of https://github.com/YosysHQ/yosys.git
27 lines
682 B
Plaintext
27 lines
682 B
Plaintext
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read_verilog <<EOT
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module top ( out, clk, reset );
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk)
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if (reset)
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out <= 8'b0;
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else
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out <= out + 1;
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endmodule
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EOT
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 7 t:LUT3
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select -assert-count 4 t:LUT4
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select -assert-count 8 t:LUTFF
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select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUTFF %% t:* %D
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