mirror of https://github.com/YosysHQ/yosys.git
10 lines
125 B
Verilog
10 lines
125 B
Verilog
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`include "common_sim.vh"
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`include "ccu2d_sim.vh"
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`ifndef NO_INCLUDES
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`include "cells_ff.vh"
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`include "cells_io.vh"
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`endif
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