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14 lines
286 B
Verilog
14 lines
286 B
Verilog
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// Demo for "final" smtc constraints
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module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);
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always @(posedge clk) begin
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if (rst) begin
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r1 <= in;
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r2 <= -in;
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end else begin
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r1 <= r1 + in;
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r2 <= inv2 ? -(r2 - in) : (r2 - in);
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end
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end
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endmodule
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