mirror of https://github.com/YosysHQ/yosys.git
15 lines
170 B
Verilog
15 lines
170 B
Verilog
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module example(
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input wire CLK,
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output wire [7:0] LED
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);
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reg [27:0] ctr;
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initial ctr = 0;
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always @(posedge CLK)
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ctr <= ctr + 1;
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assign LED = ctr[27:20];
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endmodule
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