mirror of https://github.com/YosysHQ/yosys.git
36 lines
738 B
Verilog
36 lines
738 B
Verilog
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`default_nettype none
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module lfsr_updown (
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clk , // Clock input
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reset , // Reset input
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enable , // Enable input
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up_down , // Up Down input
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count , // Count output
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overflow // Overflow output
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);
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input clk;
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input reset;
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input enable;
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input up_down;
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output [7 : 0] count;
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output overflow;
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reg [7 : 0] count;
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assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) :
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(count == {1'b1, {7{1'b0}}}) ;
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always @(posedge clk)
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if (reset)
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count <= {7{1'b0}};
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else if (enable) begin
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if (up_down) begin
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count <= {~(^(count & 8'b01100011)),count[7:1]};
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end else begin
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count <= {count[5:0],~(^(count & 8'b10110001))};
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end
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end
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endmodule
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