83 lines
3.3 KiB
ReStructuredText
83 lines
3.3 KiB
ReStructuredText
Very High Voltage Methodology
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=============================
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Very High Voltage is defined as a voltage outside the range of GND to High Voltage (11V). Very high voltage is 16V (12V nominal) Vcc.
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Any device that is subjected to a voltage outside the range of GND to 11V is considered a Very High Voltage (VHV) device.
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These devices are subjected to special design rules and biasing conditions.
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Failure Mechanisms in VHV Devices
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---------------------------------
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The TDR have a special rules section for the layout and DRC of the VHV device.
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These rules are framed so as to prevent the following failure mechanisms in
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circuits that use these devices:
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Transistor Performance Degradation under VHV Gate Stress
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The maximum voltage across the gate oxide (gate to channel voltage) is restricted to:
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a. Any VHV NMOS device: 5.5V.
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b. Any VHV PMOS device: 5.5V.
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Junction Leakage/breakdown
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The maximum source/drain to substrate junction voltages are restricted to the following:
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a. Any VHV NMOS device: 16.0V.
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b. Any VHV PMOS device: 16.0V.
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Gated-Diode Leakage/Breakdown:
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All VHV devices use 110A gate oxide thickness just like standard 5.0V Vcc devices.
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The maximum gate-to-junction voltage differentials should not exceed the voltage criteria set by conditions (1) and (2) above.
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The VHV devices need to be designed with drain extentions (DE) fabricated by lightly doped Nwells and Pwellsrespectively. Under no circumstances the poly/extended drain overlap and field oxide length should be changed.
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Source to Drain Punch-through
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To prevent punch-through, the VHV devices have expanded channel lengths:
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a. VHV NMOS device channel length = 1.055 um drawn.
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b. VHV PMOS device channel length = 1.050 um drawn.
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Parasitic Isolation Field Leakage
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Poly from a drain extended device is prohibited from forming gates with adjacent hv diffusions.
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Sub-threshold EndCap Leakage
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The extension of poly forming a high voltage gate onto field to prevent subthreshold leakage due to line-end shortening of the poly/field oxide endcap.
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Reliability performance:
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In order to preserve the reliability performance of the VHV FETs the Field Oxide (STI) length may not be changed from the values below:
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a. VHV NMOS STI length = 1.585 um
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b. VHV PMOS STI length = 1.190 um
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A poly gate may never be directly connected to a VHV diffusion region.
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Poly connecting two VHV nodes over field must be routed through LI or metal.
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VHV Implementation Methodology
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------------------------------
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Following are the features of the VHV rules:
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* All features operating at 16V (max) voltages can be Very-High-Voltage (VHV)
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* Drain or source of the drain-extended device can be tagged with vhvi:dg layer. Device with either drain or source (not both) tagged with vhvi:dg layer serves as propagation stopper
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* The VHVSourceDrain can be connected to another VHVSourceDrain or an output pad. The VHVSourceDrain does not propagate the VHV through the device
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* All source/drains/gate tagged with vhvi:dg propagate VHV through any interconnects.
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* Diff inside areaid.ed on the same net as VHVSourceDrain should be tagged with vhvi:dg. They serve as propagation stopper.
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* Deep N-well, N-well, P-well, Diff, or Poly cannot be used as routing layers.
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.. csv-table:: Table 2 - Truth table for very high voltage generation, propagation and retention.
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:file: hv/table-2.csv
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:header-rows: 1
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.. include:: hv/table-2-key.rst
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