skywater-pdk/docs/rules/periphery/p050-denmos_dotdash.csv

1.1 KiB

1NameDescriptionFlagsValueUnit
2(denmos.1)Min width of de_nFet_gate1.055µm
3(denmos.2)Min width of de_nFet_source not overlapping poly0.280µm
4(denmos.3)Min width of de_nFet_source overlapping poly0.925µm
5(denmos.4)Min width of the de_nFet_drain0.170µm
6(denmos.5)Min/Max extension of de_nFet_source over nwell0.225
7(denmos.6)Min/Max spacing between de_nFet_drain and de_nFet_source1.585µm
8(denmos.7)Min channel width for de_nFet_gate5.000µm
9(denmos.8)90 degree angles are not permitted for nwell overlapping de_nFET_drain
10(denmos.9a)All bevels on nwell are 45 degree, 0.43 µm from cornersNCµm
11(denmos.9b)All bevels on de_nFet_drain are 45 degree, 0.05 µm from cornersNCµm
12(denmos.10)Min enclosure of de_nFet_drain by nwell0.660µm
13(denmos.11)Min spacing between p+ tap and (nwell overlapping de_nFet_drain)0.860µm
14(denmos.12)Min spacing between nwells overlapping de_nFET_drain2.400µm
15(denmos.13)de_nFet_source must be enclosed by nsdm by0.130µm
16(denmos.14)nvhv FETs must be enclosed by :drc_tag:`areaid.mt`N/AN/A